1. Field of the Invention
This invention relates generally to the field of dielectric layers employed within microelectronics fabrications, and more particularly to methods for forming silicon oxide dielectric layers for inter-level metal layer separation within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications employ dielectric layers for electrical isolation and separation of conductive layers used to interconnect circuits within the microelectronics fabrication. When multiple levels of conductor layers are required to interconnect the high density of devices currently being fabricated within microelectronics fabrications, their separation is accomplished by inter-level metal dielectric (IMO) layers.
Silicon containing dielectric materials may be formed into inter-level metal dielectric (IMD) layers useful for employment in microelectronics fabrications by chemical vapor deposition (CVD) methods. In particular, silicon oxide dielectric layers formed by plasma enhanced chemical vapor deposition (PECVD) methods are well suited for these purposes because of the high quality of the physical and electrical properties of such materials. On the other hand, silicon oxide dielectric layers formed by ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods are of lesser quality but generally form planarized, rather than conformal, gap filling layers having reasonably smooth, flat surfaces suitable for further photolithographic pattern formation processes. The degree of formation of voids or defects in silicon oxide dielectric layers formed by SACVD methods is determined by various forms of surface treatment prior to deposition. For example, the exposure of an underlying surface of a silicon containing dielectric layer to a plasma treatment often minimizes formation of voids in the subsequently deposited silicon oxide layer.
As the dimensions of features employed in microelectronics fabrications continue to diminish, the need for deposited dielectric layers to fill in narrow gaps without formation of voids or other defects has exceeded the capability of conventional methods for forming gap filling silicon oxide dielectric layer to fulfill the requirements without problems being encountered, in particular with respect to inter-level dielectric layers formed employing SACVD methods having sufficiently good quality dielectric properties suitable for formation thereon of further patterned microelectronics conductor layers.
It is therefore towards the goal of forming inter-level metal (IMD) dielectric layers employing silicon oxide dielectric layers with improved gap filling formed by chemical vapor deposition (CVD) methods that the present invention is more generally directed.
Various methods have been disclosed within the art of microelectronics fabrication for forming upon a substrate employed within a microelectronics fabrication an inter-level metal dielectric (IMD) layer upon and between patterned microelectronics layers.
For example, Lee, in U.S. Pat. No. 5,605,859, discloses a method for forming a dielectric layer over a polysilicon resistor layer while employing plasma enhanced chemical vapor deposition (PECVD) from silane to form a silicon oxide dielectric layer. The polysilicon layer has already been formed upon a glasseous dielectric layer, so that the silicon oxide layer is deposited partly over the glasseous layer.
Further, Yang, in U.S. Pat. No. 5,656,556, discloses a method for forming a planar insulating layer comprising four layers of borophosphosilicate glass, each formed with different doping concentrations of boron and phosphorus so that the corresponding temperatures vary from higher for the first layer to lower temperatures for succeeding layers. The final layer employs low doping concentrations to enable it to function as a capping layer to minimize moisture absorption by the lower layers.
Still further, Ahlburn, in U.S. Pat. No. 5,650,359, discloses a composite dielectric layer for final passivation of an integrated circuit. The layer first employs TEOS in a PECVD process to form a silicon oxide layer 2000 angstroms thick, followed by SACVD in O.sub.3 -TEOS to form a second layer of silicon oxide 8000 angstroms thick, and then a silicon nitride layer formed by CVD process to a thickness of 10,000 angstroms.
Yet still further, Jang et al., in U.S. Pat. No. 5,731,241, disclose a method for forming a protective dielectric layer over a trench oxide layer to prevent over-etching of the trench oxide layer. The protective dielectric layer is formed employing O.sub.3 -TEOS in a SACVD method.
Yet further still, Jang et al., in U.S. Pat. No. 5,741,740, disclose a method for forming a dielectric layer for shallow trench isolation (STI) wherein a conformal silicon oxide layer is first formed in the trench employing silane in a PECVD process, and then a gap filling silicon oxide is formed over the trench and conformal first silicon oxide layer employing SACVD in O.sub.3 -TEOS.
Still yet further, Cronin et al., in U.S. Pat. No. 5,773,361, disclose a method for forming microcavities within dielectric layers. The method employs a void-forming dielectric material such as borophosphosilicate glass (BPSG) formed over a substrate having topography such that voids will form in a desired location. A second layer having a greater density than the void-forming material is then formed over the void-forming material. After suitable annealing such as Rapid Thermal Anneal (RTA), the dielectric layer is chemical mechanical polish (CMP) planarized to expose the top of the void. Anisotropic etching is then employed to remove sufficient void-forming material to form a contact via hole.
Finally, Fry, in U.S. Pat. No. 5,786,278, discloses a method for changing the tensile stress in a dielectric layer formed employing O.sub.3 -TEOS in a SACVD process to a compressive stress. The method employs exposure of the silicon oxide dielectric layer to pressures above atmospheric pressure at temperatures below the stress conversion temperature for the dielectric layer at atmospheric pressure to bring about the conversion of stress.
Desirable in the art of microelectronics fabrication are additional methods for forming upon a substrate within a microelectronics fabrication an inter-level metal dielectric (IMD) layer formed between and upon patterned conductor layers. More particularly desirable in the art of microelectronics fabrication are methods for forming upon a substrate within a microelectronics fabrication an inter-level metal dielectric layer employing silicon oxide dielectric materials formed with controlled void content disposed around patterned conductor layers.
It is towards the foregoing goals that the present invention is generally and more specifically directed.